The invention relates generally to integrated circuits and, in particular, the invention relates to the use of alloys for producing metal interconnects in integrated circuits.
As the density of semiconductor devices continues to increase, the need for smaller interconnections also increases. Historically, the semiconductor industry has used a subtractive etching process to pattern metal interconnect layers of the semiconductor. This metal processing technique, however, has limitations including poor step coverage, non-planarity, shorts and other fabrication problems. To address these problems, a dual damascene technique has been developed. This process, as explained in xe2x80x9cDual Damascene: A ULSI Wiring Technologyxe2x80x9d, Kaanta et al., 1991 VMIC Conference, 144-150 (Jun. 11-12, 1991) and incorporated herein by reference, involves the deposition of a metal into contact vias and conductor trenches which are patterned in the semiconductor. The semiconductor is then subjected to a known CMP (chemical-mechanical polish) process to both planarize the semiconductor and to remove excess metal from all but the patterned areas.
The metal layer can be fabricated using known CVD (chemical vapor deposition) or PVD (physical vapor deposition) techniques. Filling the patterned structures formed during the dual damascene technique, however, has proved difficult. This difficulty is exaggerated as the aspect ratio (depth to width) of the patterns increase. As such, the use of high pressure to achieve improved fill in sub-micron conductor processing for ULSI integrated circuits has received considerable attention recently. One of the problems encountered is that high temperatures must be combined with high pressure to achieve conditions where sufficient metal flow will take place to fill the narrow troughs in the damascene process.
During the metal deposition process, an aluminum alloy which may contain such elements as copper and silicon, is deposited on the integrated circuit wafer. Aluminum has been typically used due to its low resistance and good adhesion to SiO2 and Si. Silicon is usually added as an alloying element to alleviate junction spiking in Al contacts to Si. Further, electromigration and hillocks (spike-like formations) can be reduced by adding Cu, Ti, Pd or Si to aluminum to form alloys. These alloying elements precipitate at the grain boundaries. Thus, the grain boundaries are xe2x80x9cpluggedxe2x80x9d and vacancy migration is inhibited.
As interconnects become smaller, the electrical properties of the interconnect become more critical. Resistance of the interconnect rises as the cross-sectional area decreases. As resistance rises, performance of the integrated circuit decreases and power consumption rises.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alloys which can be used to fill high aspect ratio structures in an integrated circuit and that have improved electrical properties. Specifically, alloys and alloy systems are needed which will enable force fill to be achieved with improved electrical properties over the standard Al-0.5% Cu alloy which is used by much of the industry.
The above-mentioned problems with metal interconnect alloys in an integrated circuit and other problems are addressed by the invention, and which will be understood by reading and studying the following specification. Interconnect alloys are described which facilitate the use of the Group 1B transition metals, i.e., gold, silver and copper, in the fabrication of high aspect ratio features. Group 1B transition metals have improved electrical characteristics over aluminum. In particular, the invention describes interconnect alloys for use in an integrated circuit, wherein the interconnect alloys have copper, silver or gold as their major constituent element. Unless otherwise noted, alloy composition percentages refer to weight percent of the total alloy.
The invention provide alloy systems and methods for use in the fabrication of integrated circuits, dies, modules and systems. The alloys of the invention facilitate filling high aspect ratio features using force filling of a dual damascene process, wherein the interconnects have improved electrical properties over the standard Al-0.5% Cu alloy used by much of the industry.
In one embodiment, an alloy has a Group 1B transition metal as the major constituent element. The alloy further contains at least one additional element having less than approximately 2% solubility by weight in the Group 1B transition metal at approximately 100xc2x0 C., wherein each at least one additional element individually produces a eutectic temperature with the Group 1B transition metal of more than 90xc2x0 C. below the melting point of the pure Group 1B transition metal. In another embodiment, the at least one additional element individually produces a eutectic temperature with the Group 1B transition metal of more than 300xc2x0 C. below the melting point of the pure Group 1B transition metal. In a further embodiment, the at least one additional element individually produces a eutectic temperature with the Group 1B transition metal of more than 600xc2x0 C. below the melting point of the pure Group 1B transition metal.
In one embodiment, an alloy has copper as the major constituent element. The alloy further contains one or more of the elements titanium, zirconium, hafnium, lithium, magnesium and phosphorous.
In another embodiment, an alloy has silver as the major constituent element. The alloy further contains one or more of the elements beryllium, bismuth, germanium, lead and silicon.
In a further embodiment, an alloy has gold as the major constituent element. The alloy further contains one or more of the elements bismuth, cobalt, germanium, lead, antimony and silicon.
In one embodiment, an alloy has copper as the major constituent element. The alloy further contains two or more of the elements magnesium, phosphorous, titanium, hafnium and zirconium in a ternary, quaternary or higher order eutectic system having a eutectic temperature of less than approximately 714xc2x0 C.
In another embodiment, an alloy has silver as the major constituent element with approximately 1.6 to 2.6% by weight of bismuth and less than approximately 1% by weight of silicon. In yet another embodiment, the alloy is subjected to a heat treatment after filling. In still another embodiment, the alloy is subjected to a heat treatment after filling, wherein the heat treatment comprises exposing the alloy to temperatures of approximately 150xc2x0 C. for a period of time from approximately one to twenty hours.
In another embodiment, an alloy has gold as the major constituent element with approximately 0.5 to 1.5% by weight each of one or more of the elements bismuth, lead, antimony and silicon.
In a further embodiment, a method of fabricating an integrated circuit interconnect is described. The method comprises forming contact vias and interconnect trenches in an insulator layer, depositing a metal alloy in the contact vias and interconnect trenches, and removing excess metal alloy to provide defined interconnects. The alloy comprises an inventive alloy as described herein.
In a still further embodiment, an integrated circuit memory device is provided which comprises an array of memory cells, internal circuitry, and interconnects coupled to the array of memory cells and internal circuitry. At least one of the interconnects comprises an inventive alloy as described herein.
In another embodiment, the invention provides a semiconductor die having a memory device contained thereon, the memory device comprising an array of memory cells, internal circuitry, and interconnects coupled to the array of memory cells and internal circuitry. At least one of the interconnects comprises an inventive alloy as described herein.
In yet another embodiment, the invention provides a circuit module having a memory device contained therein, the memory device comprising an array of memory cells, internal circuitry, and interconnects coupled to the array of memory cells and internal circuitry. At least one of the interconnects comprises an inventive alloy as described herein.
In another embodiment, the invention provides an electronic system having a memory device contained therein, the memory device comprising an array of memory cells, internal circuitry, and interconnects coupled to the array of memory cells and internal circuitry. At least one of the interconnects comprises an inventive alloy as described herein.